The above-referenced United States patent applications are hereby incorporated herein by reference in their entirety.
After a very large scale integrated circuit (VLSIC) has been designed and optimized in simulation according to particular specifications, an actual circuit is tested to ensure that there are no defects (e.g., physical defects, component defects, circuital defects, etc.) in the VLSIC.
A conventional scan chain provides a system and a method for testing for defects in, for example, sequential devices and combinational logic circuits of the VLSIC. In a conventional scan chain, the sequential devices (e.g., flip flops or flops) of the VLSIC are connected into a serial chain as shown, in part, in FIG. 1. The VLSIC includes sequential devices 10, 20 and combinational logic circuits 30. The conventional scan chain system consists of many flops, however only two of the flops are shown for illustration. A first flop 10 and a second flop 20 have inputs and outputs. In the illustrated example, each flop 10, 20 has a data input DI, a scan input SI, a clock input CLK and a data output DO. The data input DI is connected to combinational logic circuit 30 of the VLSIC. The clock input CLK is connected to a clock of the VLSIC (not shown). The data output DO is connected to the combinational logic circuit 30.
In addition, the data output DO of the first flop 10 is also connected to a buffer 40 via a first wire 50. The buffer 40 is connected to the scan input SI of the second flop 20 via a second wire 60. The scan input SI of the first flop 10 is connected such that it receives the scan output signal from the data output DO of the previous flop (not shown) in the serial chain via a buffer (not shown) and two wires (not shown). The data output DO of the second flop 20 is also connected to the next flop (not shown) in the serial chain via a buffer (not shown) and two wires (not shown) such that the next flop receives the scan output signal from the second flop 20.
In operation, an input test vector is scanned through the serial chain of flops. The input test vector is a known set of zeroes and ones. The input test vector is scanned in serially one bit at a time through the serial chain. The scan path in the illustrated example passes through the scan input SI of the first flop 10, the data output DO of the first flop, the first wire 50, the buffer 40, the second wire 60, the scan input SI of the second flop 20, the data output DO of the second flop and so on. The buffer 40 provides a needed time delay between the data output DO of the first flop 10 and the scan input SI of the second flop 20 so that the second flop 20 can function properly. The time delay is needed, for example, to avoid hold time violations or other time violations from occurring in the second flop 20. When a time violation occurs, the output of the flop is not necessarily known for a given input. Such time delays have become more prominent in scan chain design as technologies become smaller and faster.
Once the entire input test vector has been scanned (i.e., shifted) into the serial chain such that each flop of the serial chain has its associated value from the input test vector, the data input signals to the flops are loaded in parallel via the data inputs DI of the flops. The input signals to the flops may be a function of at least one of the combinational logic circuit 30 and the values on the data outputs DO of the flops. The data input signals then pass to the data outputs DO of the flops. The data outputs DO then are scanned out or shifted out to form another set of zeroes and ones known as an output test vector. The output test vector can then be compared with the expected test vector to determine whether a defect occurs in the VLSIC. The expected test vector may have been generated from a simulation program.
This conventional example may have one or more of the following disadvantages. For example, before the testing, the VLSIC was already designed and optimized to satisfy the particular specifications. However, in order to make the scan chain, changes in the VLSIC must be made which may push the performance of the VLSIC out of compliance with the specifications. For example, to perform the scan chain, a buffer needs to be inserted near the first flop 10 and the second flop 20. Furthermore, two wires 50, 60 need to be added to connect the buffer 40 to the flops 10, 20. Combinational logic circuits may need to be rearranged and wires will need to be broken and rewired to avoid the buffers and the additional two wires per buffer.
In addition, the timing of the VLSIC may be altered by the scan chain. For example, buffers may be placed where space is available in the VLSIC, but far away from the flops they serve. Thus, a substantial amount of delay may be added to the timing of the circuit which may cause the circuit to malfunction. In addition, if the buffers are spaced far away from the flops, then this can cause unwanted wiring complexities in the VLSIC to accommodate the buffer wiring. The timing of the flops is also affected by the scan chain. For example, the data output DO of the first flop 10 is loaded by at least the additional wire 50 and the buffer 40 which will affect the first flop 10 during functional operation.
The effects of making the scan chain are magnified significantly in light of the fact that a VLSIC may contain hundreds of thousands or millions of flops. This can be very frustrating for a design engineer since before making the scan chain, most of the value had already been invested in the design and the optimizing of the design of the VLSIC. Then, merely to test the physical circuit for defects via a scan chain, the design had to be significantly revised to accommodate the additional buffers and the two wires associated with each buffer.
A cycle results in connecting the scan chain, followed by fixing the design which was broken by adding the scan chain, which may lead to reconnecting the scan chain broken by the fixes, followed by fixing the design again and so on. This cycle may add a lot of time and require a lot of resources to complete a VLSIC, which previous to testing may have functioned effectively. The time added may be dependent upon the complexity of the design and may be on the order of days, weeks or months.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.